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IS61VPS25672A - 18Mb Single CYCLE DESELECT STATIC RAM

Download the IS61VPS25672A datasheet PDF. This datasheet also covers the IS61LPS102418A variant, as both devices belong to the same 18mb single cycle deselect static ram family and are provided as variant models within a single manufacturer datasheet.

Description

and IS61LPS/VPS25672A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth ex- pansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Single cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JTAG Boundary Scan.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61LPS102418A_IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61VPS25618EC SINGLE CYCLE DESELECT SRAM ISSI
IS61VPS25636A Single CYCLE DESELECT STATIC RAM ISSI
IS61VPS25636B 9Mb Single CYCLE DESELECT STATIC RAM ISSI
IS61VPS204818B 36Mb Single CYCLE DESELECT STATIC RAM ISSI
IS61VPS102436B 36Mb Single CYCLE DESELECT STATIC RAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61VPS25618A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM
IS61VPS204818A 36Mb Single CYCLE DESELECT STATIC RAM
IS61VPS102418A 18Mb Single CYCLE DESELECT STATIC RAM
IS61VPS102418B SINGLE CYCLE DESELECT STATIC RAM
IS61VPS102436A 36Mb Single CYCLE DESELECT STATIC RAM

Full PDF Text Transcription

Click to expand full text
IS61vPS25672A IS61lPS25672A IS61vPS51236A IS61lPS51236A IS61vPS102418A IS61lPS102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM JULY 2017 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth ex- pansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.
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