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IS61NVP102436A - 36Mb STATE BUS SRAM

Download the IS61NVP102436A datasheet PDF. This datasheet also covers the IS61NVP204818A variant, as both devices belong to the same 36mb state bus sram family and are provided as variant models within a single manufacturer datasheet.

Description

The 36 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.

Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle.
  • Individual Byte Write Control.
  • Single R/W (Read/Write) control pin.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control using MODE input.
  • Three chip enables for simple depth expansion and address pipelining.
  • Power Down mode.
  • Common data inputs and data output.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61NVP204818A_IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61NVP102418 (IS61NVPxxxxx) STATE BUS SRAM ISSI
IS61NVP102418B 18Mb STATE BUS SYNCHRONOUS SRAM ISSI
IS61NVP10018 (IS61NVP10018 / IS61NVP51236) State Bus SRAM ISSI
IS61NVP12818A (IS61NVPxxxxxA) STATE BUS SRAM ISSI
IS61NVP12836A (IS61NVPxxxxxA) STATE BUS SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NVP204818A 36Mb STATE BUS SRAM
IS61NVP204836B PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP409618B PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVF102418 STATE BUS SRAM
IS61NVF204836B FLOW THROUGH (NO WAIT) STATE BUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A 1Mb x 36 and 2Mb x 18 36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEBRUARY 2012 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP package • Power supply: NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.
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