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IS61NLF204836B - FLOW THROUGH (NO WAIT) STATE BUS SRAM

Description

The 72 Meg product family

Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle.
  • Individual Byte Write Control.
  • Single Read/Write control pin.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control us- ing MODE input.
  • Three chip enables for simple depth expansion and address pipelining.
  • Power Down mode.
  • Common data inputs and da.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NLF409618B FLOW THROUGH (NO WAIT) STATE BUS SRAM
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IS61NLP204818A 36Mb STATE BUS SRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61NLF204836B/IS61NVF/NVVF204836B IS61NLF409618B/IS61NVF/NVVF409618B  2M x 36 and 4M x 18 72Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM ADVANCED INFORMATION FEBRUARY 2013 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 119-ball PBGA, and 165- ball PBGA packages • Power supply: NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVF: Vdd 2.
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