Datasheet4U Logo Datasheet4U.com

IS61DDP2B42M36A2 - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM

Download the IS61DDP2B42M36A2 datasheet PDF (IS61DDP2B44M18A included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 72mb ddr-iip cio synchronous sram.

Description

2Mx36 and 4Mx18 configuration available.

valid window.

Common I/O read and write ports.

operation.

Double Data Rate (DDR) interface for read and write input ports.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDP2B44M18A-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Other Datasheets by Integrated Silicon Solution

Full PDF Text Transcription

Click to expand full text
IS61DDP2B44M18A/A1/A2 IS61DDP2B42M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75 to 0.9V VREF.
Published: |