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IS61DDB21M18A - 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM

Description

The 18Mb IS61DDB251236A and IS61DDB21M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Features

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only.
  • Two input clocks (C and C#.

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📁 Similar Datasheet

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDB21M36 DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB21M36A 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB22M18 DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M18A 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB22M36 DDR-II (Burst of 2) CIO Synchronous SRAMs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61DDB21M18A IS61DDB251236A 1Mx18, 512Kx36 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM OCTOBER 2014 FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two input clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.  HSTL input and output interface.
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