IS46R32800F sdram equivalent, 256mb ddr sdram.
DEVICE OVERVIEW
* VDD and VDDQ: 2.5V ± 0.2V
* SSTL_2 compatible I/O
* Double-data rate architecture; two data transfers
per clock cycle
* Bidirectio.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
x8
A0-A12
Row Address Input
A0-A9
Column Address Input
BA0, BA1
Bank Select Address
DQ0
– DQ7
Data I/O
CK, CK
System Clock Input
CKE
Clock Enable
CS Chip Select
CAS
Column Address Strobe Command
RAS
Row Address Strob.
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