IDTVP386 Overview
The VP386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.8 Gbps throughput or 350 Mbytes per second. This chip is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces through very low-swing LVDS signals.
IDTVP386 Key Features
- Wide clock frequency range from 20 MHz to 100 MHz
- Pin patible with the National DS90CF386, THine
- Fully spread spectrum patible
- LVDS voltage swing of 350 mV for low EMI
- On-chip PLL requires no external ponents
- Low-power CMOS design
- Falling edge clock triggered outputs
- Power-down control function
- patible with TIA/EIA-644 LVDS standards
- Packaged in a 56-pin TSSOP (Pb free available)