Network Search Engine 64K x 72 Entries
Datasheet Brief 75P52100
s Full Ternary 64K x 72 bit content addressable memory
s Upgradeable to 128K x 72 NSE
s Power Management
s Global Mask Registers
s 100M sustained lookups per second at 72 and 144 width lookups
s Burst write for high speed table updates
s Learn new entries
s Dual bus interface
s Cascadable to 8 devices with no glue logic or latency penalty
s Glueless interface to standard ZBT™ or
Synchronous Pipelined Burst SRAMs
s Boundary Scan JTAG Interface (IEEE 1149.1compliant)
s 1.8V core power supply
s 2.5V VBIAS power supply
s User selectable 2.5V or 1.8V I/O supply
s SRAM No Wait
An SRAM No Wait
can be pipelined within a series of operations and does not require the user
to wait for the Read to complete before loading the next instruction.
s Dual Write
In addition to individual writes, the NSE has the ability to perform
simultaneous writes to a Data entry and a respective external SRAM
Alookupcanberequestedin72-bit,144-bit, 288-bit or 576-bitwidths.
A 36-bit lookup can be accomplished by using two Global Mask Registers.
The NSE implements a fully autonomous Learn Instruction, which
provides a mechanism for the user to write a lookup entry into an unused
the user to update an entry into the NSE which had not previously been
stored. The Learn writes the new entry, making it available for future
The NSE provides all required address and control signals for a
glueless SRAM interface. The NSE provides a pipelined bypass path for
reads or writes to the external SRAM. The ASIC/FPGA handles the
pipelining of the data to and from the SRAM.
Data and Mask Array
The NSE has Data cell entries and associ-
combination of Data and Mask cell entries en-
ables the NSE to store 0, 1 or X, making it a full
ternary Network Search Engine. During a
lookup operation, both arrays are used along
with a Global Mask Register to find a match to a
requested data word.
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There are four basic types of registers supported:
s Configuration Registers are used at initialization to define the
segmentation of the entries, timing of outputs and the SRAM interface.
s Global Mask Registers are provided to support Lookup
instructions by masking individual bits during a search.
s Comparand Registers assist in the Learn Instruction.
s Result Registers are used to store the resulting index of a search
from a Lookup or Learn operation.
The NSE utilizes a dual bus interface consisting of the NSE Request
Bus and the NSE Response Bus.
The NSE Request Bus is comprised of the Command Bus and the
while the Request Data Bus is the main data path to the NSE.
The 72 bit bi-directional Request Data Bus functions as a multiplexed
address and data bus, which performs the writing and reading of NSE
entries, as well as presenting lookup data to the device.
The NSE Response Bus is comprised of an independent unidirec-
tional Index Bus which drives the result of the lookup (or index) to either
an SRAM device or an ASIC. In addition to driving the Index, the NSE
Response Bus also drives the associated SRAM control signals (CE/OE,
andWE)foreitherZBT™ orSynchronousPipelineBurst SRAMdevices.
The Command Bus loads the specific instructions into the NSE. These
s Read or Write
A Read or Write instruction operates on a specified data entry, mask
entry, or register.
Synchronous Burst Write
The burst write feature has no limit on the number of continuous write
accesses and supports initialization of the NSE.
Width Segmentation Capability
The NSEs are capable of performing lookups for comparisons on data
structures of 72 bits, 144 bits, 288 bits and 576 bits. These devices has
can be configured to meet various system requirements.
s Single Width Array
s Multiple Width Arrays within a Single Device
The Multi-Match feature signals to the user that more than one match
has resulted. The result of the lookup, which defines the highest priority
match, is sent along with the Multi-Match signal.
Power Savings and Classification Features
See the full IDT75P52100 Datasheet for more information.