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Integrated Device Technology Electronic Components Datasheet

IDT75P52100 Datasheet

NETWORK SEARCH ENGINE 64K x 72 Entries

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NETWORK SEARCH ENGINE
64K x 72 Entries
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Brief
75P52100
To request the full IDT75P52100 datasheet, please contact your local
IDT Sales Representative or call 1-831-754-4555
Device Description
IDT provides proven, industry-leading network search engines
(NSEs) and a comprehensive suite of software that enable and accelerate
the intelligent processing of network services in communications equip-
ment. As a part of the complete IDT classification subsystem that includes
content inspection engines, the IDT family of NSEs delivers high-
performance, feature-rich, easy-to-use, integrated search accelerators.
TheIDT 75P52100NSEisahighperformancepipelinedlow-power,
synchronous full-ternary 64K x 72 entry device. Each entry location in
the NSE has both a Data entry and an associated Mask entry. The NSE
devices integrate content addressable memory (CAM) technology with
high-performancelogic. ThedevicecanperformLookupandLearnNSE
operations plus Read, Write, Burst Write, and Dual Write maintenance
operations.
The IDT 75P52100 NSE device has a bi-directional bus that is a
multiplexed address and data bus that can support 100 million sustained
searches per second. This device provides array segments which can
be configured to enable multiple width lookups from 36 to 576 bits wide.
The IDT 75P52100 requires a 1.8-volt VDD supply, a user selectable 1.8
or 2.5-volt VDDQ supply, and a 2.5-volt VBIAS supply. This NSE device
provides the user with flexibility and control in determining the device
power. Only the array segments that will be used for a specific NSE
operation are powered up while the unused segments are not.
The IDT 75P52100 utilizes IDT’s latest high-performance 1.8V
CMOS processing technology and is packaged in a JEDEC Standard,
thermally enhanced, low profile Ball Grid Array. The options include a
304 BGA, satisfying smaller footprint requirements and a 372 BGA
package that is compatible with IDT's 32K x 72 Entry (75P42100) and
128K x 72 Entry (75P62100) NSE devices.
Block Diagram
LAST NSE
LAST SRAM
CLOCK
PHASE
÷2
BURST
Counter
RESET
CCLK
REQSTB
Command
Bus
NSE
REQUEST
BUS
Request
Data
Bus
Instruction
R/W
Address
D
E
C
O
D
E
Configuration Registers
and
Ram Control Circuits
P
R
SI
IO
ZR
EI
ARRAY
T
LY
O
GE
IN
CC
O
D
E
R
Bypass
DATA
Comparand Registers
Global Mask Registers
Result Register
5333 drw 01
SRAM CONTROL
ASIC FEEDBACK
Index
Bus
NSE
RESPONSE
BUS
MMOUT
MATCHOUT
System Configurations
The IDT NSEs are designed to fulfill the needs of various types of
networking systems. In solutions requiring data searching such as
routers, a system configuration as shown in Figure 1.0 may be realized.
Maximum flexibility is provided by allowing one board design to be
populated today using either the IDT 75P42100 or 75P52100 NSEs and
later upgraded to use IDT’s 75K62100 NSE. Applications note AN-279
discusses how to accommodate one board design for any of these NSEs.
In this compatible configuration, the NSE interfaces directly to an
ASIC/ FPGA for lookups and routes an Index to an associated SRAM
device, which supplies the next hop address via an SRAM Data Bus to
the ASIC. The NSE provides the required control signals to directly
hookuptoZBT™orSynchronousPipelineBurstSRAM. Lookupresults
can also be fed directly back to the ASIC/ FPGA without the use of external
SRAM. Control of the associated handshake signals is provided by all
NSEs to adapt to either configuration.
Figure 1.0 ASIC / Compatible NSE / SRAM configuration
ASIC
or
FPGA
IDT
75P42100
or
75P52100
or
75K62100
Network Search Engine
Optional
ZBT
or
Sync SRAM
5333 drw02
JUNE 2003
1
© 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5333/03


Integrated Device Technology Electronic Components Datasheet

IDT75P52100 Datasheet

NETWORK SEARCH ENGINE 64K x 72 Entries

No Preview Available !

Network Search Engine 64K x 72 Entries
Datasheet Brief 75P52100
Features
s Full Ternary 64K x 72 bit content addressable memory
s Upgradeable to 128K x 72 NSE
s Power Management
s Global Mask Registers
s Segmentsindividuallyconfigurable
s 36/72/144/288/576multiplewidthlookups
s 100M sustained lookups per second at 72 and 144 width lookups
s Burst write for high speed table updates
s Multi-match
s Learn new entries
s Dual bus interface
s Cascadable to 8 devices with no glue logic or latency penalty
s Glueless interface to standard ZBT™ or
Synchronous Pipelined Burst SRAMs
s Boundary Scan JTAG Interface (IEEE 1149.1compliant)
s 1.8V core power supply
s 2.5V VBIAS power supply
s User selectable 2.5V or 1.8V I/O supply
Functional Highlights
s SRAM No Wait
An SRAM No Wait
Read
Read is
a
Read
instruction
to
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can be pipelined within a series of operations and does not require the user
to wait for the Read to complete before loading the next instruction.
s Dual Write
In addition to individual writes, the NSE has the ability to perform
simultaneous writes to a Data entry and a respective external SRAM
location.
s Lookup
Alookupcanberequestedin72-bit,144-bit, 288-bit or 576-bitwidths.
A 36-bit lookup can be accomplished by using two Global Mask Registers.
s Learn
The NSE implements a fully autonomous Learn Instruction, which
provides a mechanism for the user to write a lookup entry into an unused
locationintheNSEandtheassociateddatainexternalSRAM. Thisallows
the user to update an entry into the NSE which had not previously been
stored. The Learn writes the new entry, making it available for future
lookups.
SRAM Interface
The NSE provides all required address and control signals for a
glueless SRAM interface. The NSE provides a pipelined bypass path for
reads or writes to the external SRAM. The ASIC/FPGA handles the
pipelining of the data to and from the SRAM.
Data and Mask Array
The NSE has Data cell entries and associ-
atedMaskcellentriesasshowninFig.1.1. This
combination of Data and Mask cell entries en-
ables the NSE to store 0, 1 or X, making it a full
ternary Network Search Engine. During a
lookup operation, both arrays are used along
with a Global Mask Register to find a match to a
requested data word.
Figure 1.1
Mask
Data
A 5333 drw 03
Registers
There are four basic types of registers supported:
s Configuration Registers are used at initialization to define the
segmentation of the entries, timing of outputs and the SRAM interface.
s Global Mask Registers are provided to support Lookup
instructions by masking individual bits during a search.
s Comparand Registers assist in the Learn Instruction.
s Result Registers are used to store the resulting index of a search
from a Lookup or Learn operation.
Bus Interface
The NSE utilizes a dual bus interface consisting of the NSE Request
Bus and the NSE Response Bus.
The NSE Request Bus is comprised of the Command Bus and the
RequestDataBus. TheCommandBushandlestheinstructiontotheNSE
while the Request Data Bus is the main data path to the NSE.
The 72 bit bi-directional Request Data Bus functions as a multiplexed
address and data bus, which performs the writing and reading of NSE
entries, as well as presenting lookup data to the device.
The NSE Response Bus is comprised of an independent unidirec-
tional Index Bus which drives the result of the lookup (or index) to either
an SRAM device or an ASIC. In addition to driving the Index, the NSE
Response Bus also drives the associated SRAM control signals (CE/OE,
andWE)foreitherZBT™ orSynchronousPipelineBurst SRAMdevices.
Command Bus
The Command Bus loads the specific instructions into the NSE. These
include:
s Read or Write
A Read or Write instruction operates on a specified data entry, mask
entry, or register.
Synchronous Burst Write
The burst write feature has no limit on the number of continuous write
accesses and supports initialization of the NSE.
Width Segmentation Capability
The NSEs are capable of performing lookups for comparisons on data
structures of 72 bits, 144 bits, 288 bits and 576 bits. These devices has
can be configured to meet various system requirements.
s Single Width Array
s Multiple Width Arrays within a Single Device
Multi Match
The Multi-Match feature signals to the user that more than one match
has resulted. The result of the lookup, which defines the highest priority
match, is sent along with the Multi-Match signal.
Power Savings and Classification Features
See the full IDT75P52100 Datasheet for more information.
2


Part Number IDT75P52100
Description NETWORK SEARCH ENGINE 64K x 72 Entries
Maker Integrated Device Technology
Total Page 3 Pages
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