IDT72T3675 Datasheet | Integrated Device Technology

.. 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 and 262,144 x 36 IDT72T3645, IDT72T3655, IDT72T3665, IDT72T3675, IDT72T3685, IDT72T3695, IDT72T36105, IDT72T36115, IDT72T36125 Features : - - - - - - - - - - - - - Choose among the following memory organizations: IDT72T3645  1,024 x 36 IDT72T3655  2,048 x 36 IDT72T3665  4,096 x 36 IDT72T3675  8,192 x 36 IDT72T3685  16,384 x 36 IDT72T3695  32,768 x 36 IDT72T36105  65,536 x 36 IDT72T36115  131,072 x 36 IDT72T36125  262,144 x 36 Up to 225 MHz Operation of Clocks User selectable HSTL/LVTTL Input and/or Output 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage 3.3V Input tolerant Read Enable & Read Clock Echo outputs aid high speed operation User selectable Asynchronous read and/or write port timing Mark & Retransmit, resets read pointer to user marked position Write Chip Select (WCS) input enables/disables Write operations Read Chip Select (RCS) synchronous to RCLK Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Program programmable flags by either serial or parallel means Selectable synchronous/asynchronous timing modes for Almost- - - - - - - - - - - - - - - - Empty and Almost-Full flags Separate SCLK input for Serial programming of flag offsets User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out Big-Endian/Little-Endian user selectable byte representation Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and...