900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Integrated Device Technology Electronic Components Datasheet

IDT72P51569 Datasheet

1.8V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION

No Preview Available !

1.8V MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION
589,824 bits
1,179,648 bits
2,359,296 bits
4,718,592 bits
ADVANCE INFORMATION
www.DIDaTta7S2hPe5e1t54U3.9com
IDT72P51549
IDT72P51559
IDT72P51569
FEATURES
Choose from among the following memory density options:
IDT72P51539 Total Available Memory = 589,824 bits
IDT72P51549 Total Available Memory = 1,179,648 bits
IDT72P51559 Total Available Memory = 2,359,296 bits
IDT72P51569 Total Available Memory = 4,718,592 bits
Configurable from 1 to 32 Queues
Default configuration of 32 or 16 symmetrical queues
Default multi-queue device configurations
– IDT72P51539: 512 x 36 x 32Q
– IDT72P51549: 1,024 x 36 x 32Q
– IDT72P51559: 2,048 x 36 x 32Q
– IDT72P51569: 4,096 x 36 x 32Q
Default configuration can be augmented via the queue address
bus
Number of queues and individual queue sizes may be
configured at master reset though serial programming
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Independent Read and Write access per queue
User Selectable Bus Matching Options:
– x36 in to x36 out – x18 in to x36 out
– x9 in to x36 out
– x36in to x18out
– x18 in to x18 out
– x9 in to x18 out
– x36in to x9out
– x18 in to x9 out
– x9 in to x9 out
User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL
100% Bus Utilization, Read and Write on every clock cycle
Selectable First Word Fall Through (FWFT) or IDT standard
mode of operation
Ability to operate on packet or word boundaries
Mark and Re-Write operation
Mark and Re-Read operation
Individual, Active queue flags (OR / EF, IR / FF, PAE, PAF, PR)
8 bit parallel flag status on both read and write ports
Direct or polled operation of flag status bus
Expansion of up to 256 queues and/or 32Mb logical configura-
tion using up to 8 multi-queue devices in parallel
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
WADEN
FSTR
WRADD
WEN 8
WCLK
WCS
Din
x36, 18 or x9
DATA IN
FF/IR
PAF
PAFn
8
Q31
Q30
Q29
Q0
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RADEN
ESTR
RDADD
8 REN
RCLK
RCS
OE
Qout
x36, x18 or x9
DATA OUT
EF/OR
PR
PAE
PAEn
8 PRn
6715 drw01
SEPTEMBER 2004
DSC-6715/-


Integrated Device Technology Electronic Components Datasheet

IDT72P51569 Datasheet

1.8V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION

No Preview Available !

IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
Table of Contents
www.DataSheet4U.com
Features ........................................................................................................................................................................................................................ 1
Description ................................................................................................................................................................................................................... 5
Pin configuration ......................................................................................................................................................................................................... 7
Detailed Description .................................................................................................................................................................................................... 8
Pin Descriptions ......................................................................................................................................................................................................... 10
Pin number table ........................................................................................................................................................................................................ 16
Recommended DC operating conditions ................................................................................................................................................................ 17
Absolute maximum ratings ........................................................................................................................................................................................ 17
DC electrical characteristics ..................................................................................................................................................................................... 18
AC electrical characteristics ...................................................................................................................................................................................... 20
Functional description .............................................................................................................................................................................................. 22
Serial Programming .............................................................................................................................................................................................. 23
Default Programming ............................................................................................................................................................................................ 23
Parallel Programming ........................................................................................................................................................................................... 23
Queue Description ..................................................................................................................................................................................................... 25
Configuration of the IDT Multi-queue flow-control device ....................................................................................................................................... 25
Standard mode operation ..................................................................................................................................................................................... 26
Read Queue Selection and Read Operation ......................................................................................................................................................... 27
Switching Queues on the Write Port ...................................................................................................................................................................... 29
Switching Queues on the Read Port ..................................................................................................................................................................... 31
Flag Description ......................................................................................................................................................................................................... 42
PAFn Flag Bus Operation ..................................................................................................................................................................................... 42
Full Flag Operation ............................................................................................................................................................................................... 42
Empty or Output Ready Flag Operation (EF/OR) .................................................................................................................................................. 42
Almost Full Flag .................................................................................................................................................................................................... 43
Almost Empty Flag ................................................................................................................................................................................................ 43
Packet Ready Flag ............................................................................................................................................................................................... 47
Packet Mode Demarcation bits .............................................................................................................................................................................. 49
JTAG Interface ............................................................................................................................................................................................................ 82
JTAG AC electrical characteristics ............................................................................................................................................................................ 86
Ordering Information ................................................................................................................................................................................................. 87
List of Tables
Table 1 — Device programming mode comparison ........................................................................................................................................................ 22
Table 2 — Setting the queue programming mode during master reset ............................................................................................................................. 22
Table 3 — Mode Configuration ...................................................................................................................................................................................... 25
Table 4 — Write Address Bus, WRADD[7:0] ................................................................................................................................................................... 26
Table 5 — Read Address Bus, RDADD[7:0] .................................................................................................................................................................. 27
Table 6 — Write Queue Switch Operation ...................................................................................................................................................................... 30
Table 7 — Read Queue Switch Operation ..................................................................................................................................................................... 32
Table 8 — Same Queue Switch ..................................................................................................................................................................................... 32
Table 9 — Flag operation boundaries and Timing .......................................................................................................................................................... 45
Table 10 — Packet Mode Valid Byte for x36 bit word configuration ................................................................................................................................. 48
Table 11 — Bus-Matching Set-Up .................................................................................................................................................................................. 52
2 SEPTEMBER 27, 2004


Part Number IDT72P51569
Description 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION
Maker Integrated Device Technology
Total Page 30 Pages
PDF Download

IDT72P51569 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 IDT72P51569 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION
Integrated Device Technology





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy