ICS9LPRS535 - 48-pin CK505

Integrated Device Technology

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Datasheet Details

Part number	ICS9LPRS535
Manufacturer	Integrated Device Technology
File Size	254.12 KB
Description	48-pin CK505
Datasheet	ICS9LPRS535_IntegratedDeviceTechnology.pdf

ICS9LPRS535 Product details

Description

PIN # 1 2 3 PIN NAME PCI0/CR#_A VDDPCI PCI4/SRC5_EN TYPE DESCRIPTION 4 5 6 7 8 9 10 PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOT96T_LPR/SRCT0_LPR 3.3V PCI clock output or CR#_A input.Default is PCI0. To configure this pin as CR#_A, the PCI output must first be disabled in Byte 2, bit 0. I/O Byte 5, bit 7: 0 = PCI0 enabled (default), 1= CR#_A enabled.Byte 5, bit 6: 0 = CR#_A controls SRC0 (default), 1= CR#_A# controls SRC2. PWR Power supply for PCI clocks, nominal 3.3V 3.3

Features

Integrated Series Resistors on differential outputs.
2 - CPU differential push-pull pairs.
4 - SRC differential push-pull pairs.
1 - CPU/SRC selectable differential push-pull pair.
1 - SRC/DOT selectable differential push-pull pair.
1- SRC/Stop_Inputs selectable differential push-pull pair.
1 - 25MHz SE1 output for Wake-on-Lan.

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Published: Apr 11, 2010 |