ICS87421I Datasheet PDF - Integrated Device Technology DIFFERENTIAL-TO-LVDS CLOCK GENERATOR Specs

ICS87421I - DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

Datasheet Summary

Description

The ICS87421I is a high perfor mance ÷1/÷2 IC S Differential-to-LVDS Clock Generator and a memHiPerClockS™ ber of the HiPerClockS™ family of High Performance Clock Solutions from IDT.

The CLK, nCLK pair can accept most standard differential input levels.

Features

One differential LVDS output.
One differential CLK, nCLK input pair.
CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
Maximum clock input frequency: 1GHz.
Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS levels with resistor bias on nCLK input.
Part-to-part skew: 500ps (maximum).
Propagation delay: 1.7ns (maximum).
Additive phase jitter, RMS @ 155.52MH.

Datasheet Details

Part number	ICS87421I
Manufacturer	Integrated Device Technology
File Size	285.31 KB
Description	DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
Datasheet	ICS87421I Datasheet
Additional preview pages of the ICS87421I datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR ICS87421I GENERAL DESCRIPTION The ICS87421I is a high perfor mance ÷1/÷2 IC S Differential-to-LVDS Clock Generator and a memHiPerClockS™ ber of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The ICS87421I is characterized to operate from a 3.3V power supply. Guaranteed part-to-part skew characteristics make the ICS87421I ideal for those clock distribution applications demanding well defined performance and repeatability.

Published: May 3, 2010 |