ICS854S058I multiplexer equivalent, 8:1 differential-to-lvds clock multiplexer.
* High speed 8:1 differential multiplexer
* One differential LVDS output pair
* Eight selectable differential PCLK, nPCLK input pairs
* PCLKx, nPCLKx pair.
Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental.
The ICS854S058I is an 8:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz. The ICS854S058I has 8 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, SSTL or CML levels. The fully differenti.
Image gallery
TAGS
Download