Description
for EJTAG/JTAG pins in Table 1.
WEN signals, and deleted old footnote #3 and chang
Features
- 32-bit CPU Core.
- MIPS32 instruction set.
- Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches.
- 16 dual-entry JTLB with variable page sizes.
- 3-entry instruction TLB www. DataSheet4U. com.
- 3-entry data TLB.
- Max issue rate of one 32x16 multiply per clock.
- Max issue rate of one 32x32 multiply every other clock.
- CPU control with start, stop and single stepping.
- S.
79RC32K438_IntegratedDeviceTechnology.pdf
