79RC32438 processor equivalent, idttm interprisetm integrated communications processor.
32-bit CPU Core
– MIPS32 instruction set
– Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-b.
that require integer arithmetic. The CPU core includes 16 KB instruction and 16 KB data caches. Both caches are 4-way se.
for EJTAG/JTAG pins in Table 1. Changed DDRDM[7:0] from input/output to output only in Tables 1 and 2 and Logic Diagram. Added new section, Voltage Sense Signal Timing, as part of EJTAG description. March 4, 2003: In Table 2, removed “pull-up” from P.
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