ICS9DB104 Datasheet | Integrated Circuit Systems

Features : - 4 - 0.7V current-mode differential output pairs - Supports zero delay buffer mode and fanout mode - Bandwidth programming available Key Specifications: - Outputs cycle-cycle jitter: < 50ps - Outputs skew: < 50ps - +/- 300ppm frequency accuracy on output clocks Features /Benefits: - Supports tight ppm accuracy clocks for Serial-ATA - Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread - Supports undriven differential output pair in PD# and SRC_STOP# for power management. Pin Configuration VDD SRC_IN SRC_IN# GND VDD DIF_1 DIF_1# OE_1 DIF_2 DIF_2# VDD BYPASS#/PLL SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDA GNDA IREF GND VDD DIF_6 DIF_6# OE_6 DIF_5 DIF_5# VDD HIGH_BW# SRC_STOP# PD# 28-pin SSOP & TSSOP 0767C- 07/19/04 Data Sheet 4 U . .. Integrated Circuit Systems, Inc. Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME VDD SRC_IN SRC_IN# GND VDD DIF_1 DIF_1# OE_1 DIF_2 DIF_2# VDD BYPASS#/PLL SCLK SDATA PD# SRC_STOP# HIGH_BW# VDD DIF_5# DIF_5 OE_6 DIF_6# DIF_6 VDD GND IREF GNDA VDDA PIN TYPE PWR IN IN PWR PWR OUT OUT IN OUT OUT PWR IN IN I/O IN IN IN PWR OUT OUT IN OUT OUT PWR PWR OUT PWR PWR DESCRIPTION Power supply, nominal 3.3V 0.7 V Differential SRC TRUE input 0.7 V Differential SRC PLEMENTARY input Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential plement clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential plement clock outputs Power supply, nominal 3.3V Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Asynchronous active low input pin used to power down the device. The internal clocks are disabled and the VCO and the crystal are...