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Integrated Circuit Systems

ICS8MJ0 Datasheet Preview

ICS8MJ0 Datasheet

(ICS8Mx0) Crystal Oscillator

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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8Mx0
Crystal Oscillator: LVCMOS/LVTTL CLOCK OUTPUT
ICS8Mx0
LOW JITTER, HIGH FREQUENCY XTAL OSCILLATOR
Stable, ultra low jitter, LVCMOS/LVTTL clock generation
For Gigabit Ethernet, Fibre Channel, PCI-Express, other applications
Clock output frequencies from 75 to 250 MHz
One single-ended LVCMOS/LVTTL clock output
Output Enable (OE) pin (tri-state when low)
Small 4-pin 5 x 7 x 1.5mm SMT ceramic package
Low profile package allows back-side PCB mounting
Pb-free RoHS compliant (by default; no additional code required)
2.5V or 3.3V device power supply options
Commercial (0 to +70 OC) and Industrial (-40 to +85 OC) temperatures
Frequency stability of ±50 or ±100 ppm
(including initial accuracy, operating temperature variation,
supply voltage variation, load variation, reflow drift, and aging for 10 years)
Low phase jitter < 1 ps rms maximum (12kHz to 20MHz)
8Mx0
(Top View)
4-pin CERHERMETIC 5 x 7 x 1.5mm SMT
ELECTRICAL SPECIFICATIONS
Unless stated otherwise, VDD = 3.3 Volts + 0.3V or 2.5 Volts + 5%, TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), CL < 25pF
Parameter
Min Typ Max Unit
Conditions
DC CHARACTERISTICS
Power Supply Voltage
Power Supply
(VDD pin)
Power Supply Current
VDD 3.0 3.3 3.6 V
2.375
2.5
2.625 V
3.3V operation
2.5V operation
in 8MJ0 and 8MK0 only
IDD 75 mA
OE = VDD
Current with Output Disable IOED
<0.6 mA
OE = GND
Input Capacitance
CIN
4 pF
Output Enable Input High Voltage
(OE pin)
LVCMOS/LVTTL Input Low Voltage
VIH 0.7 x VDD
VIL
V
0.3 x VDD V
Input High Current
IIH
5 µA
VDD = VIN = 3.6V or 2.625V
Input Low Current
IIL -150
µA VDD = 3.6V or 2.625V, VIN = 0V
Internal Pull-up Resistor
RPULLUP
51
k
Output High Voltage1
Clock Output
VOH
Level
Output Low Voltage1
VOL
(OUT pin)
LVCMOS/LVTTL Output Load Condition (fan out) CL
VDD - 0.4
V
0.4 V
25 pF
VDD = 3.3V + 0.3V or 2.5V + 5%
fO < 250MHz
Output Impedance
ROUT
5
7
12
AC CHARACTERISTICS
Output Frequency Range
Output
(OUT pin)
Frequency Stability error
f/fO
75
250
±100
±50
MHz
ppm p-p in 8MH0 and 8MK0
ppm p-p in 8MG0 and 8MJ0
All conditions
Includes frequency set,
VDD, TA & load variation,
reflow drift, 10 yr. aging
Output Duty Cycle
odc
Output Rise Time
Output Fall Time
Oscillator Start-up Time
tR
tF
tOSC
RMS Phase Jitter, (Random) 2 t jit(Ø)
50 %
1.5 ns
1.5 ns
10 ms
< 1 ps rms
design target
VTH = VDD / 2 , CL < Max. pF
20% to 80% of VDD , CL < Max. pF
Time at Min. VDD (3.0V or 2.375V) to be 0s
(design target)
Jitter tDS 2 0.2 ps Deterministic
tRS 3
3
ps Random
σ of Random jitter
tRMS 3
3 ps Root Mean Square σ of Total jitter distribution
tP-P 3
25 ps Peak to Peak
tacc 3
4
ps Accumulated Jitter
n = 2 to 50,000 cycles
Note 1: Outputs terminated with 50to VDD / 2. See PARAMETER MEASUREMENT INFORMATION, Output Load AC Test Circuit diagrams.
Note 2: Measured using an Aeroflex PN9500 with a 12 kHz to 20MHz integration range.
Note 3: Measured using a Wavecrest SIA-3000.
SUPPLY VOLTAGE & FREQUENCY ACCURACY
G = 3.3V
±50 ppm
H = 3.3V ± 100 ppm
J = 3.3/2.5V
± 50 ppm
K = 3.3/2.5V ± 100 ppm
ICS8Mx0 Datasheet Rev A
Revised 30Nov2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400




Integrated Circuit Systems

ICS8MJ0 Datasheet Preview

ICS8MJ0 Datasheet

(ICS8Mx0) Crystal Oscillator

No Preview Available !

www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
PIN DESCRIPTIONS
1 OE
Input
Internal pull-up resistor
Output enable pin.
LVCMOS/LVTTL interface levels.
2 GND Power
Power supply ground.
3 OUT Output No internal terminator
Single-ended clock output.
LVCMOS/LVTTL interface levels.
4 VDD Power
Power supply pin.
For typical value of internal pull-up resistor, see DC Characteristics.
PARAMETER MEASUREMENT INFORMATION
1.65V±5
ICS8MX0
Crystal Oscillator: LVCMOS/LVTTL CLOCK OUTPUT
PRELIMINARY
Inputs
ABSOLUTE MAXIMUM RATINGS
VI -0.5 to VDD +0.5
V
Outputs
VO
Positive Supply Voltage
VDD
Package Thermal Impedence
-0.5 to VDD +0.5
4.6
TBD
V
V
°C/W (0 lfpm)
Storage Temperature
TS
-40 to +100
oC
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed in DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
1.25V±5
VDD
LVCMOS
GND
SCOPE
Qx
VDD
LVCMOS
GND
SCOPE
Qx
-1.65V±5%
3.3V Output Load AC Test Circuit
Phase Noise Plot
-1.25V±5%
2.5V Output Load AC Test Circuit
OUT
VDD
2
odc =
tPW
tPERIOD
tPW
(Output Pulse Width)
tPERIOD
Output Duty Cycle
f1 Offset Frequency f2
RMS Jitter = Area Under Offset Frequency Markers
RMS Phase Jitter
APPLICATION INFORMATION
VDD
U1
R1
43
80%
80%
20%
Clock
Output
tR
tF
Output Rise and Fall Time
20%
Zo = 50
Receiv er_lv cmos
8MXO
OE
VDD
C1
10uf
C2
.1uf
VDD
Zo = 50
R2
100
R3
100
Receiv er_lv cmos
OptiOopntioanlal TTeermrminiantioantion
LVCMOS Application Schematic / Power Supply Filtering (Decoupling Circuit)
ICS8Mx0 Datasheet Rev A
2 of 3
Revised 30Nov2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400


Part Number ICS8MJ0
Description (ICS8Mx0) Crystal Oscillator
Maker Integrated Circuit Systems
Total Page 3 Pages
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