ICS840004 Datasheet | Integrated Circuit Systems

DESCRIPTION The ICS840004 is a 4 output LVCMOS/LVTTL IC S Synthesizer optimized to generate Ether net Hi Per Clock S™ reference clock frequencies and is a member of the Hi Per Clocks TM family of high performance clock solutions from IDT. Using a 26.5625MHz, 18p F parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and .. 53.125MHz. The ICS840004 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random r ms phase jitter, easily meeting Ethernet jitter requirements. The ICS840004 is packaged in a small 20-pin TSSOP package. FEATURES - Four LVCMOS/LVTTL outputs, 17Ω typical output impedance - Selectable crystal oscillator interface or LVCMOS single-ended input - Supports the following input frequencies: 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz - VCO range: 560MHz - 700MHz - RMS phase jitter @ 212.5MHz (637k Hz - 10MHz): 0.49ps typical, VDDO = 3.3V Phase noise: Offset Noise Power 100Hz -88.8 d Bc/Hz 1k Hz -109.0 d Bc/Hz 10k Hz -116.1 d Bc/Hz 100k Hz -117.5 d Bc/Hz - Full 3.3V or mixed 3.3V core/2.5V output supply mode - 0°C to 70°C ambient operating temperature - Available in both standard (Ro HS 5) and lead-free (Ro HS 6) packages FREQUENCY SELECT FUNCTION TABLE Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 26.04166 Inputs M Divider F_SEL0 Value 0 24 1 0 1 1 24 24 24 24 N Divider Value 3 4 6 12 4 F_SEL1 0 0 1 1 0 M/N Ratio Value 8 6 4 2 6 Output Frequency Range (MHz) 212.5 159.375 106.25 53.125 (default) 156.25 BLOCK DIAGRAM OE Pullup F_SEL1:0 Pullup:Pullup n PLL_SEL Pulldown n XTAL_SEL Pulldown PIN ASSIGNMENT F_SEL0 nc n XTAL_SEL REF_CLK OE MR n PLL_SEL VDDA nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT XTAL_IN 26.5625MHz XTAL_OUT REF_CLK Pulldown F_SEL1:0 1 Phase...