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ICS650R-27 - Networking Clock Source

Download the ICS650R-27 datasheet PDF. This datasheet also covers the ICS650-27 variant, as both devices belong to the same networking clock source family and are provided as variant models within a single manufacturer datasheet.

General Description

The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications.

Key Features

  • Packaged in 20-pin (150 mil) SSOP (QSOP).
  • Available in Pb (lead) free package.
  • 12.5 MHz or 25 MHz fundamental crystal or clock.
  • input Six output clocks with selectable frequencies SDRAM frequencies of 67, 83, 100, and 133 MHz Buffered crystal reference output Zero ppm synthesis error in all clocks Ideal for PMC-Sierra’s ATM switch chips Full CMOS output swing with 25 mA output dri.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ICS650-27_IntegratedCircuitSystems.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ICS650R-27
Manufacturer Integrated Circuit Systems
File Size Direct Link
Description Networking Clock Source
Datasheet download datasheet ICS650R-27 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS650-01 SYSTEM PERIPHERAL CLOCK SOURCE Renesas
ICS650-07C NETWORKING CLOCK SOURCE Renesas
ICS650-11 NETWORKING CLOCK SYNTHESIZER IDT
ICS650-14 NETWORKING SYSTEM CLOCK Renesas
ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE Renesas

Other Datasheets by Integrated Circuit Systems

Part Number Description
ICS650R-21 System Peripheral Clock Source
ICS650R-22 PVR and STB Clock Source
ICS650R-01 System Peripheral Clock Source
ICS650R-05 HDTV Clock Synthesizer
ICS650R-07B Broadcom Clock Source

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ICS650-27 Networking Clock Source Description The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-27 outputs all have zero ppm synthesis error. The ICS650-27 is pin compatible and functionally equivalent to the ICS650-07. It is a performance upgrade and is recommended for all new 3.3V designs. See the MK74CB214, ICS551, and ICS552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks.