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* Packaged in 16 pin narrow (150 mil) SOIC Input clock up to 160 MHz in the non-PLL mode Provides clock outputs of CLK, CLK, and CLK/2 L.

that to need maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) mode should be used. This chip is no.

The ICS548-03 is a low cost, low skew, high performance general-purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-2. Using our patented analog Phase-Locked Loop (PLL) techniques, the devi.

ICS548-05A

ICS548A-03

ICS541

ICS542

ICS543

ICS544-01

ICS501

ICS501A

ICS501B

ICS502

ICS503

ICS507-xx

ICS508

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