ICS513 Datasheet | Integrated Circuit Systems

Features - Packaged as 8 pin SOIC - ICS’ lowest cost PLL clock plus reference - Produces mon puter frequencies - Input crystal frequency typically 14.3182 MHz - Output clock frequencies up to 100 MHz - Low jitter - 40 ps one sigma - patible with all popular CPUs - Duty cycle of 45/55 - Custom frequencies available - Operating voltages of 3.0 to 5.5 V - Power down mode turns off chip - 25m A drive capability at TTL levels - Advanced, low power CMOS process Description The ICS513 LOCO™ is the most cost effective way to generate a high quality, high frequency clock output from a 14.31818 MHz crystal or clock input. The name LOCO stands for LOw Cost Oscillator, as it is designed to replace crystal oscillators in many electronic systems. Using Phase-Locked-Loop (PLL) techniques, the device uses a standard, inexpensive crystal to produce output clocks up to 100 MHz. Stored in the chip’s ROM is the ability to generate 5 different output frequencies, allowing one chip to work in different speed processor systems. The device also has a power down mode that turns off the clock outputs when both select pins are low. In this mode, the internal PLL is not running. Block Diagram VDD GND 2 S1, S0 PLL Clock Synthesis and Control Circuitry Output Buffer CLK 14.31818 MHz crystal or clock X1/ICLK Crystal Oscillator X2 Output Buffer Optional crystal capacitors 1 Revision 080699 Printed 12/4/00 Integrated Circuit Systems - 525 Race Street - San Jose - CA- 95126 - (408)295-9800tel- (408)295-9818fax MDS 513 B .. ICS513 LOCO™ PLL Clock Generator Pin Assignment X1/ICLK VDD GND REF 1 2 3 4 8 7 6 5 X2 S1 S0 CLK Clock Decoding Table (MHz) with 14.31818MHz Crystal or Clock Input S1 0 0 M M 1 1 S0 0 1 0 1 0 1 CLK Multiplier Power Down CLK 100 6.984 24 1.676 14.31818 1 48 3.353 3.6864 0.2576 Accuracy 1 ppm 1 ppm 0 ppm 0.017% 0.044% 0 = connect directly to ground. 1 = connect directly to VDD. M = leave unconnected (floating). CLK and REF stop low in power down state. Pin...