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Integrated Circuit Systems

ICS1889 Datasheet Preview

ICS1889 Datasheet

100Base-FX Integrated PHYceiverTM

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Integrated
Circuit
Systems, Inc.
ICS1889
100Base-FX Integrated PHYceiverTM
General Description
The ICS1889 is a fully integrated physical layer device
supporting 100 Megabits per second CSMA/CD Fast
Ethernet fiber optic applications. It is designed to support
the requirements of DTEs (adapter cards), repeaters and
switches. It is compliant with the ISO/IEC 8802 Fast
Ethernet standard for 100Base-FX. It provides a Media
Independent Interface (MII) allowing direct chip-to-chip
connection, motherboard-to-daughter board connection or
connection via a cable in a similar manner to the AUI
approach used with 10Base-Tsystems. A station
management interface is provided to receive command
information and send status information. It transmits and
receives NRZI data and interfaces directly to the optical
transceiver. It can operate in either half duplex or full
duplex.
Features
• One chip integrated physical layer
• All CMOS, low power design
• ISO/IEC 8802-3 CSMA/CD compliant
• 100Base-FX Half & Full Duplex
• Far end fault detection
• Media Independent Interface (MII)
• Station management interface
• Extended register set including QuickPollTM detailed
status monitoring
• Transmit clock synthesis
• Receive clock and data recovery
• Detailed receive error reporting
• Extended Test Modes
• 52-pin MQFP package with 2.0 mil body thickness
Block Diagram
ICS1889RevF092497P
PHYceiver and QuickPoll are trademarks of Integrated Circuit Systems, Inc.




Integrated Circuit Systems

ICS1889 Datasheet Preview

ICS1889 Datasheet

100Base-FX Integrated PHYceiverTM

No Preview Available !

ICS1889
Block Diagram
Functional Description
Introduction
The ICS1889 is a nibble to bit stream and bit stream to nibble
processor. When transmitting, it takes sequential nibbles
presented at the Media Independent Interface (MII) and
translates them to a serial bit stream for transmission on the
media. When receiving, it takes the serial bit stream from the
media and translates it to sequential nibbles for presentation
to the MII. It has no knowledge of the underlying structure of
the MAC frame it is conveying.
When transmitting, the ICS1889 encapsulates the MAC
frame (including the preamble) with the start-of-stream
(SSD) and end-of-stream (ESD) delimiters. When receiving,
it strips off the SSD and substitutes the normal preamble
pattern and then presents this and subsequent preamble
nibbles to the MII. When it encounters the ESD it ends the
presentation of nibbles to the MII. Thus, the MAC
reconciliation layer sees an exact copy of the transmitted
frame.
During periods when no frames are being transmitted or
received, there is a requirement to signal and detect the idle
condition. This allows the higher levels to determine the
integrity of the connection between the node and the hub. A
continuous stream of ones is transmitted to signify the idle
condition, the receive channel includes logic that monitors
the IDLE data stream to look for this pattern and thereby
establish the link integrity.
2


Part Number ICS1889
Description 100Base-FX Integrated PHYceiverTM
Maker Integrated Circuit Systems
Total Page 30 Pages
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