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Integrated Circuit Systems

ICS1887 Datasheet Preview

ICS1887 Datasheet

FDDI / Fast Ethernet PHYceiverTM

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Integrated
Circuit
Systems, Inc.
ICS1887
FDDI / Fast Ethernet PHYceiverTM
General Description
Features
The ICS1887 is designed to provide high performance clock • Single IC solution to existing designs requiring
recovery and generation for 125 MHz serial data streams. The
multiple devices
ICS1887 is ideally suited for LAN transceiver applications in • Data and clock recovery for 125 MBaud FDDI or Fast
either FDDI or Fast Ethernet environments. The ICS1887
Ethernet applications
converts NRZ to/from NRZI data in addition to providing a • Clock multiplication from either a crystal, differential
5-bit parallel digital data transmit and receive interface.
or single-ended timing source
Clock and data recovery is performed on an input serial data • Continuous clock in the absence of data
stream or the buffered transmit data depending upon the state • No external PLL components
of the loopback input. A continuous clock source will • Lock/Loss status indicator output
continue to be present even in the absence of input data. • Loopback mode for system diagnostics
All internal timing is derived from either a low cost crystal,
differential or single-ended source.
Selectable loop timing mode
• PECL driver with settable sink current
The ICS1887 utilizes advanced CMOS phase-locked loop • Parallel digital transmit and receive data interface
technology which combines high performance and low power • NRZ to/from NRZI data conversion
at a greatly reduced cost.
• Consult ICS for optional configurations and data rates
Block Diagram
Pin Configuration
ICS1887RevF112596
28-Pin SOIC
PHYceiver is a trademark of Integrated Circuit Systems, Inc.




Integrated Circuit Systems

ICS1887 Datasheet Preview

ICS1887 Datasheet

FDDI / Fast Ethernet PHYceiverTM

No Preview Available !

ICS1887
Pin Descriptions
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
VSS
TXOFF~2
CD~
TX+
TX–
VSS
IPRG1
RX–
RX+
LB~
LOCK
RD4
RD3
VSS
RD2
RD1
RD0
RCLK
VDD
REF_IN
REF_OUT
VDD
TCLK
TD0
TD1
TD2
TD3
TD4
* Active Low Input.
TYPE
TTL-Compatible
TTL-Compatible1
PECL
PECL
PECL
PECL
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
TTL-Compatible
DESCRIPTION
Negative Supply Voltage
Transmitter Off*
Carrier Detect input*
Positive Transmit serial data output
Negative Transmit serial data output
Negative supply voltage
PECL Output stage current set (TX)
Negative Receive serial data input
Positive Receive serial data input
Loop Back mode select*
Lock detect output
Recovered data output 4
Recovered data output 3
Negative supply voltage
Recovered data output 2
Recovered data output 1
Recovered data output 0
Recovered Receive clock output
Positive supply voltage
Positive reference clock/crystal input
Negative reference clock/crystal output
Positive supply voltage
Transmit clock output
Transmit data input 0
Transmit data input 1
Transmit data input 2
Transmit data input 3
Transmit data input 4
Note:
1. A running production change will be made to this input in the June 1996 time frame to convert this
input from the TTL-compatible to PECL to more closely match applications requirements. See
Substituting the ICS1887 for the AMD PDR & PDT applications note for more information.
2. This pin was formerly used for Loop-Timed operation. If your design did not use loop timing, this
change does not affect you. If your application requires loop timing, please contact ICS.
2


Part Number ICS1887
Description FDDI / Fast Ethernet PHYceiverTM
Maker Integrated Circuit Systems
Total Page 14 Pages
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