ICSSSTU32866 buffer equivalent, 25-bit configurable registered buffer.
* 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
* Supports SSTL_18 JEDEC specification on data inputs and outputs
*.
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers.
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