IS61SP12832 - 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM

Integrated Circuit Solution

IS61SP12832 Datasheet Preview — Preview of IS61SP12832 PDF

Datasheet Details

Part number	IS61SP12832
Manufacturer	Integrated Circuit Solution
File Size	486.62 KB
Description	128K x 32 SYNCHRONOUS PIPELINED STATIC RAM
Datasheet	IS61SP12832-IntegratedCircuitSolution.pdf

IS61SP12832 Product details

Description

The ICSI IS61SP12832 is a high-speed, low-power synchro- nous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors.It is organized as 131,072 words by 32 bits, fabricated with ICSI's advanced CMOS technology.The device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit.All synchronous inputs pass through registers cont

Features

Internal self-timed write cycle.
Individual Byte Write Control and Global Write.
Clock controlled, registered address, data and control.
Pentium™ or linear burst sequence control using MODE input.
Three chip enables for simple depth expansion and address pipelining.
Common data inputs and data outputs.
JEDEC 100-Pin LQFP and 119-pin PBGA package.
Single +3.3V, +10%,.
5% power supply.
Power-down snooze mode.

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Published: Dec 6, 2017 |