* Clock frequency: 133 100, MHz
* Fully synchronous; all signals referenced to a positive clock edge
* Internal bank for hiding row access/precharge
* Pow.

A0-A11 A0-A8, A10 BA0, BA1 I/O0 to I/O7 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM VDD Vss VDDQ V.

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