Full PDF Text Transcription for IPSH6N03LB (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
IPSH6N03LB. For precise diagrams, and layout, please refer to the original PDF.
Type IPUH6N03LB IPSH6N03LB OptiMOS®2 Power-Transistor Package Marking • Qualified according to JEDEC1) for target applications • N-channel - Logic level • Excellent gate ...
View more extracted text
1) for target applications • N-channel - Logic level • Excellent gate charge x R DS(on) product (FOM) • Superior thermal resistance • 175 °C operating temperature • Pb-free lead plating; RoHS compliant Product Summary V DS R DS(on),max ID 30 6.
IPSH6N03LB Datasheet
