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HYB39S64160BT - 64-MBit Synchronous DRAM

Download the HYB39S64160BT datasheet PDF. This datasheet also covers the HYB39S64800BT variant, as both devices belong to the same 64-mbit synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

HYB 39S64400BT-7.5 Q67100-Q2781 HYB 39S64400BT-8 Q67100-Q1838 P-TSOP-54-2 (400mil) 133MHz 4B × 4M x4 SDRAM P-TSOP-54-2 (400mil) 125MHz 4B × 4M x4 SDRAM P-TSOP-54-2 (400mil) 133MHz 4B × 2M x8 SDRAM P-TSOP-54-2 (400mil) 125MHz 4B × 2M x8 SDRAM P-TSOP-54-2 (400mil) 133MHz 4B × 1M x16 SDRAM P-TSOP-54-

Key Features

  • CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYB39S64800BT_InfineonTechnologies.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HYB 39S64400/800/160BT(L) 64-MBit Synchronous DRAM www.DataSheet4U.com 64-MBit Synchronous DRAM • High Performance: • Multiple Burst Read with Single Write Operation Units MHz ns ns ns ns • Automatic and Controlled Precharge Command • Data Mask for Read/Write Control (x4, x8) • Data Mask for Byte Control (x16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • 4096 Refresh Cycles / 64 ms • Random Column Address every CLK (1-N Rule) • Single 3.3 V ± 0.3 V Power Supply • LVTTL Interface • Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) • -7.5 version for PC133 3-3-3 application -8 version for PC100 2-2-2 applications -7.5 -8 125 8 6 10 6 fCKMAX tCK3 tAC3 tCK2 tAC2 133 7.5 5.