CY8C4145LQI-PS423 Datasheet | Infineon

CY8C41x5 PSo C™ 4100PS Based on Arm® Cortex™-M0+ General description Infineon’ PSo C™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex®-M0+ CPU. It bines programmable and reconfigurable analog and digital blocks with flexible automatic routing. PSo C™ 4100PS is a member of the PSo C™ 4 platform architecture. It is a bination of a microcontroller with standard munication and timing peripherals, a capacitive touch-sensing system (CAPSENSE™) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. Features - Programmable analog blocks - Two dedicated analog-to-digital converters (ADC) including a 12-bit SAR ADC and a 10-bit single-slope ADC - Four opamps, two low-power parators, and a flexible 38-channel analog mux to create custom Analog Front Ends (AFE) - Two 13-bit voltage DACs - Two 7-bit current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin - CAPSENSE™ capacitive sensing - Infineon’s fourth-generation CAPSENSE™ Sigma-Delta (CSD) providing best-in-class signal-to-noise ratio (SNR) and water tolerance - Infineon-supplied software ponent makes capacitive sensing design easy - Automatic hardware tuning (Smart Sense™) - Segment LCD drive - LCD drive supported on all pins (mon or segment) - Operates in Deep-Sleep mode with four bits per pin memory - Programmable digital peripherals - Three independent serial munication blocks (SCBs) that are run-time configurable as I2C, SPI or UART - Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks with center-aligned, edge, and pseudo-random modes - 32-bit signal processing engine - Arm® Cortex®-M0+ CPU up to 48 MHz - Up to 32 KB of flash with read accelerator - Up to 4 KB of SRAM - Eight-channel descriptor-based DMA controller - Low-power operation - 1.71-V to 5.5-V operation - Deep-Sleep mode with...