CY62148G
Features
- High speed: 45 ns/55 ns
- Ultra-low standby power
- Typical standby current: 3.5 µA
- Maximum standby current: 8.7 µA
- Embedded ECC for single-bit error correction[1]
- Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
- 1.0-V data retention
- TTL-patible inputs and outputs
- Pb-free 32-pin SOIC and 32-pin TSOP II/STSOP packages
Functional description
CY62148G is a high-performance CMOS low-power (Mo BL™) SRAM device with embedded ECC[1]. This device is offered multiple pin configurations. Device is accessed by asserting the chip enable (CE) input LOW. Data writes are performed by asserting the write enable (WE) input LOW, while providing the data on I/O0 through I/O7 and address on A0 through A18 pins. Data reads are performed by asserting the output enable (OE) input and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O7). i Aslld Ie/O-ass(s Ie/Ort0edth).rough I/O7) are placed in a HI-Z state...
