G = Gate, S = Source, D = Drain, TAB = Drain G D S é (TAB)
* International standard package
* Low R HDMOS process
* Rugged polysilicon gate cell structure <.

* Switch-mode and resonant-mode Symbol Test Conditions Characteristic Values (TJ = 25°C, unless otherwise specified.

IXFJ32N50Q

IXFJ13N50

IXFJ20N85X

IXFJ40N30

IXF18102

IXF18104

IXFA102N15T

IXFA10N60P

IXFA10N80P

IXFA110N15T2

IXFA12N50P

IXFA12N65X2

IXFA130N10T

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