Datasheet4U Logo Datasheet4U.com

IS61VPS12836EC - SINGLE CYCLE DESELECT SRAM

Download the IS61VPS12836EC datasheet PDF. This datasheet also covers the IS61LPS12836EC variant, as both devices belong to the same single cycle deselect sram family and are provided as variant models within a single manufacturer datasheet.

Description

The 4Mb product family

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Single cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61LPS12836EC-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61VPS12836A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61VPS102418A 18Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61VPS102418B SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61VPS102436A 36Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61VPS204818A 36Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61VPS12832EC SINGLE CYCLE DESELECT SRAM
IS61VPS102436B 36Mb Single CYCLE DESELECT STATIC RAM
IS61VPS204818B 36Mb Single CYCLE DESELECT STATIC RAM
IS61VPS25618EC SINGLE CYCLE DESELECT SRAM
IS61VPS25636A Single CYCLE DESELECT STATIC RAM

Full PDF Text Transcription

Click to expand full text
IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM APRIL 2017 FEATURES  Internal self-timed write cycle  Individual Byte Write Control and Global Write  Clock controlled, registered address, data and control  Burst sequence control using MODE input  Three chip enable option for simple depth expansion and address pipelining  Common data inputs and data outputs  Auto Power-down during deselect  Single cycle deselect  Snooze MODE for reduced-power standby  JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages  Power supply: LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) VPS: VDD 2.5V (± 5%), VDDQ 2.
Published: |