* 2Mx36 and 4Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Separate independent read and write ports with conc.

where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.

at page 6 for each ODT option. DESCRIPTION The and are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clo.

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