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IS61QDP2B451236A1 - 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Download the IS61QDP2B451236A1 datasheet PDF. This datasheet also covers the IS61QDP2B41M18A variant, as both devices belong to the same 18mb quadp (burst 4) synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

512Kx36 and 1Mx18 configuration available.

valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) inter

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDP2B41M18A-ISSI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDP2B451236A 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B451236A2 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B451236C 18Mb QUADP SYNCHRONOUS SRAM
IS61QDP2B451236C1 18Mb QUADP SYNCHRONOUS SRAM
IS61QDP2B451236C2 18Mb QUADP SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 , 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) OCTOBER 2014 FEATURES DESCRIPTION  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support. The 18Mb IS61QDP2B451236A/A1/A2 and IS61QDP2B41M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices.
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