IS61QDB42M36C Key Features
- 2Mx36 and 4Mx18 configuration available
- Max. 400 MHz clock for high bandwidth
- Synchronous pipeline read with late write operation
- Double Data Rate (DDR) interface for read and
- 1.5 cycle read latency
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control
- Two output clocks (C and C#) for data output control
- Two echo clocks (CQ and CQ#) that are delivered