IS61QDB41M36 Datasheet, ISSI

* 1M x 36 or 2M x 18.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Separate read and write ports with concurrent read and write operations..

The 36Mb IS61QDB41M36 and IS61QDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the rea.