File Size : 476.75KB ·
1 hits
• 1M x 36 or 2M x 18.
• On-chip delay-locked loop (DLL) for wide data valid window.
• Separate read and write ports with concurrent read and write operations.
• Synchronous pipeline read with late write operation.
• Double data rate (DDR) interface for read and write input ports.
• Fixed 4-bit burst.
