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IS61QDB41M36 - 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs

Description

The 36Mb IS61QDB41M36 and IS61QDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

  • 1M x 36 or 2M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Separate read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double data rate (DDR) interface for read and write input ports.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges o.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDB41M36A 36Mb QUAD SYNCHRONOUS SRAM
IS61QDB41M18A 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
IS61QDB42M18 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs
IS61QDB42M18A 36Mb QUAD SYNCHRONOUS SRAM
IS61QDB42M36 QUAD (Burst of 4) Synchronous SRAMs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs . ISSI May 2005 ® Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation. • Double data rate (DDR) interface for read and write input ports. • Fixed 4-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two input clocks (C and C) for data output control. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.
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