IS61QDB24M18A
Description
The and are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
Key Features
- 2Mx36 and 4Mx18 configuration available.
- On-chip Delay-Locked loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with EARLY write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- Fixed 2-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only.
- Two output clocks (C and C#) for data output control.
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
