IS61QDB24M18A Datasheet PDF (72Mb QUAD (Burst 2) Synchronous SRAM)

IS61QDB24M18A - 72Mb QUAD (Burst 2) Synchronous SRAM

Description

memory (SRAM) devices.

eliminating the need for high-speed bus turnaround.

all internal operations are self-timed.

Features

2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edge.

Datasheet Details

Part number	IS61QDB24M18A
Manufacturer	ISSI
File Size	592.78 KB
Description	72Mb QUAD (Burst 2) Synchronous SRAM
Datasheet	IS61QDB24M18A Datasheet
Additional preview pages of the IS61QDB24M18A datasheet.

📁 Similar Datasheet

IS61C1024 - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C1024L - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C256 - 32K x 8 Low Voltage CMOS STATIC RAM (Integrated Silicon Solution)

IS61C25616 - 256K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)

IS61C25616AL - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C25616AS - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C256AH - 32K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C256AL - 32K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)

IS61C3216AL - 32K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C512 - 64K x 8 High Speed CMOS Static RAM (Integrated Silicon Solution)

Full PDF Text Transcription

Click to expand full text

IS61QDB24M18A IS61QDB22M36A 4Mx18, 2Mx36 72Mb QUAD (Burst 2) Synchronous SRAM AUGUST 2014 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two output clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.

Published: Jun 10, 2016 |