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IS61QDB24M18A Datasheet 72Mb QUAD (Burst 2) Synchronous SRAM

Manufacturer: ISSI (now Infineon)

Overview: IS61QDB24M18A IS61QDB22M36A 4Mx18, 2Mx36 72Mb QUAD (Burst 2) Synchronous SRAM AUGUST.

General Description

The and are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 2Mx36 and 4Mx18 configuration available.
  • On-chip Delay-Locked loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edge.