IS61NVP102418B Datasheet | ISSI

IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS SYNCHRONOUS SRAM AUGUST 2019 Features - 100 percent bus utilization - No wait cycles between Read and Write - Internal self-timed write cycle - Individual Byte Write Control - Single R/W (Read/Write) control pin - Clock controlled, registered address, data and control - Interleaved or linear burst sequence control using MODE input - Three chip enables for simple depth expansion and address pipelining - Power Down mode - mon data inputs and data outputs - /CKE pin to enable clock and suspend operation - JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages - Power supply: NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NVVP: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%) - JTAG Boundary Scan for BGA packages - mercial, Industrial and Automotive (x36) temperature support - Lead-free available - For leaded option, please contact ISSI. DESCRIPTION The 18Meg product family Features high-speed, lowpower synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and munications applications. They are organized as 512K words by 36 bits and 1024K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and highdrive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, /CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH...