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IS61DDPB24M18C - 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

Description

at page 6 for each ODT option.

The 72Mb IS61DDPB22M36C/C1/C2 and IS61DDPB24M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

Features

  • 2Mx36 and 4Mx18 configuration available.
  • Common I/O read and write ports.
  • Max. 567 MHz clock for high bandwidth.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.5 cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Two input clocks (K and K#) for address and control registering at rising edges only.
  • Two echo clocks (CQ and CQ#) that are delivere.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDPB24M18 DDR-IIP (Burst of 2) CIO Synchronous SRAMs Integrated Silicon Solution
IS61DDPB24M18A 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDPB24M18A1 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDPB24M18A2 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDPB24M18B 72Mb DDR-IIP CIO SYNCHRONOUS SRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDPB24M18C1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB24M18C2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB22M36C 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB22M36C1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB22M36C2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM

Full PDF Text Transcription

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IS61DDPB24M18C/C1/C2 IS61DDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration available.  Common I/O read and write ports.  Max. 567 MHz clock for high bandwidth  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 2-bit burst for read and write operations.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.  HSTL input and output interface.  Full data coherency.
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