IS61DDPB24M18C
Overview
The 72Mb IS61DDPB22M36C/C1/C2 and IS61DDPB24M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus.
- 2Mx36 and 4Mx18 configuration available.
- Common I/O read and write ports.
- Max. 567 MHz clock for high bandwidth
- Synchronous pipeline read with self-timed late write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- 2.5 cycle read latency.
- Fixed 2-bit burst for read and write operations.
- Two input clocks (K and K#) for address and control registering at rising edges only.
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
- +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
