IS61DDP2B21M36C2 Datasheet | ISSI

FEATURES DESCRIPTION - 1Mx36 and 2Mx18 configuration available. - mon I/O read and write ports. - Max. 500 MHz clock for high bandwidth - Synchronous pipeline read with self-timed late write operation. - Double Data Rate (DDR) interface for read and write input ports. The 36Mb IS61DDP2B21M36C/C1/C2 and IS61DDP2B22M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a mon I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are selftimed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. - 2.0 cycle read latency. - Fixed 2-bit burst for read and write operations. - Clock stop support. - Two input clocks (K and K#) for address and control registering at rising edges only. - Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. - +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: - Read/write address - Read enable - Write enable - HSTL input and output interface. - Byte writes - Registered addresses, write and read controls, byte writes, data in, and data outputs. - Full data coherency. - Boundary scan using limited set of JTAG 1149.1 functions. - Data-in for first burst address - Data-Out for first burst address The following are registered on the rising edge of the K# clock: - Byte writes - Byte write capability. - Data-in for second burst address - Fine ball grid array (FBGA) package: - Data-Out for second burst address 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array - Programmable impedance output drivers via 5x usersupplied precision resistor. - Data Valid Pin (QVLD). - ODT (On Die Termination) feature...