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IS61DDP2B21M36C2 - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM

Download the IS61DDP2B21M36C2 datasheet PDF. This datasheet also covers the IS61DDP2B22M18C variant, as both devices belong to the same 36mb ddr-iip cio synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

1Mx36 and 2Mx18 configuration available.

Common I/O read and write ports.

Max.

Synchronous pipeline read with self-timed late write operation.

Double Data Rate (DDR) interface for read and write input ports.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDP2B22M18C-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDP2B21M36A 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDP2B21M36A1 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDP2B21M36A2 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDP2B21M18A 18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDP2B21M18A1 18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDP2B21M36C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B21M36C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B22M18C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B22M18C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B22M18C2 36Mb DDR-IIP CIO SYNCHRONOUS SRAM

Full PDF Text Transcription

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IS61DDP2B22M18C/C1/C2 IS61DDP2B21M36C/C1/C2 2Mx18, 1Mx36 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) JANUARY 2017 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  Common I/O read and write ports.  Max. 500 MHz clock for high bandwidth  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports. The 36Mb IS61DDP2B21M36C/C1/C2 and IS61DDP2B22M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are selftimed.
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