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IS61DDP2B21M36C2 Datasheet

Manufacturer: ISSI (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

IS61DDP2B21M36C2 datasheet preview

Datasheet Details

Part number IS61DDP2B21M36C2
Datasheet IS61DDP2B21M36C2 IS61DDP2B22M18C Datasheet (PDF)
File Size 852.80 KB
Manufacturer ISSI (now Infineon)
Description 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B21M36C2 page 2 IS61DDP2B21M36C2 page 3

IS61DDP2B21M36C2 Overview

 1Mx36 and 2Mx18 configuration available.  mon I/O read and write ports. 500 MHz clock for high bandwidth  Synchronous pipeline read with self-timed late write operation.

IS61DDP2B21M36C2 Key Features

  • 1Mx36 and 2Mx18 configuration available
  • mon I/O read and write ports
  • Max. 500 MHz clock for high bandwidth
  • Synchronous pipeline read with self-timed late write operation
  • Double Data Rate (DDR) interface for read and write input ports
  • 2.0 cycle read latency
  • Fixed 2-bit burst for read and write operations
  • Clock stop support
  • Two input clocks (K and K#) for address and control registering at rising edges only
  • Two echo clocks (CQ and CQ#) that are delivered simultaneously with data
ISSI (now Infineon) logo - Manufacturer

More Datasheets from ISSI (now Infineon)

See all ISSI (now Infineon) datasheets

Part Number Description
IS61DDP2B21M36C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B21M36C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B22M18C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B22M18C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B22M18C2 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B41M18C 18Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B41M18C1 18Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B41M18C2 18Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B451236C 18Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B451236C1 18Mb DDR-IIP CIO SYNCHRONOUS SRAM

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