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IS46DR16640C - DDR2 DRAM

Download the IS46DR16640C datasheet PDF. This datasheet also covers the IS43DR81280C variant, as both devices belong to the same ddr2 dram family and are provided as variant models within a single manufacturer datasheet.

General Description

architecture to achieve high-speed operation.

data words per clock cycle at the I/O balls.

Key Features

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V.
  • JEDEC standard 1.8V I/O (SSTL_18-compatible).
  • Double data rate interface: two data transfers per clock cycle.
  • Differential data strobe (DQS, DQS).
  • 4-bit prefetch architecture.
  • On chip DLL to align DQ and DQS transitions with CK.
  • 8 internal banks for concurrent operation.
  • Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported.
  • Posted CAS and programmable additive laten.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS43DR81280C-ISSI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS43/46DR81280C IS43/46DR16640C 128Mx8, 64Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.