IS43R83200D sdram equivalent, ddr sdram.
* VDD and VDDQ: 2.5V ± 0.2V
* SSTL_2 compatible I/O
* Double-data rate architecture; two data transfers per clock cycle
* Bidirectional, data strobe (.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
x8
A0-A12 A0-A9 BA0, BA1 DQ0
– DQ7 CK, CK CKE CS CAS RAS WE Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Column Address Strobe Command Row Address Strobe Command Writ.
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