IS43LR32800H
Overview
The IS43/46LR32800H is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation.
- JEDEC standard 1.8V power supply.
- VDD = 1.8V, VDDQ = 1.8V
- Four internal banks for concurrent operation
- MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave)
- Fully differential clock inputs (CK, /CK)
- All inputs except data & DM are sampled at the rising edge of the system clock
- Data I/O transaction on both edges of data strobe
- Bidirectional data strobe per byte of data (DQS)
- DM for write masking only
- Edge aligned data & data strobe output
