Datasheet Details
| Part number | IS43DR81280C |
|---|---|
| Manufacturer | ISSI (now Infineon) |
| File Size | 872.14 KB |
| Description | DDR2 DRAM |
| Datasheet |
 IS43DR81280C Datasheet
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General Description
architecture to achieve high-speed operation.
data words per clock cycle at the I/O balls.
Key Features
- Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V.
- JEDEC standard 1.8V I/O (SSTL_18-compatible).
- Double data rate interface: two data transfers per clock cycle.
- Differential data strobe (DQS, DQS).
- 4-bit prefetch architecture.
- On chip DLL to align DQ and DQS transitions with CK.
- 8 internal banks for concurrent operation.
- Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported.
- Posted CAS and programmable additive laten.