IS42SM16800E Datasheet, ISSI

* Fully synchronous; all signals referenced to a positive clock edge
* Internal bank for hiding row access and precharge
* Programmable CAS latency: 2, 3 <.

Both TSOP and BGA packages are offered, including industrial grade products. KEY TIMING PARAMETERS Parameter CLK Cyc.

ISSI's 128Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 128Mb Mobil.