PZ5032-10A44 Datasheet - INTEGRATED CIRCUIT ENGINEERING

PZ5032-10A44 32 Macrocell PLD

Assembly Die Process ANALYSIS RESULTS I Assembly ANALYSIS RESULTS II Die Process TABLES Procedure Overall Quality Evaluation Package Markings Wirebond Strength Die Material Analysis Horizontal Dimensions Vertical Dimensions PAGE 1 1 2 2-3 4 5-7 8 9 10 10 10 11 12 -iFree Datasheet http://www.Da.

PZ5032-10A44 Features

* Twin-well CMOS process in an N substrate (no epi).

* Sub-micron gate lengths (0.35 micron N-channel and 0.4 micron P-channel).

* Tungsten plugs used under all metal layers. 1These items present possible quality or reliability concerns. They should be discussed with the m

PZ5032-10A44 Datasheet (5.50 MB)