PZ5032-10A44 pld equivalent, 32 macrocell pld.
* Twin-well CMOS process in an N substrate (no epi).
* Sub-micron gate lengths (0.35 micron N-channel and 0.4 micron P-channel).
* Tungsten plugs used under .
* The leadframe was constructed of copper and plated externally with tin-lead solder and internally with silver.
Assembly Die Process ANALYSIS RESULTS I Assembly ANALYSIS RESULTS II Die Process TABLES Procedure Overall Quality Evaluation Package Markings Wirebond Strength Die Material Analysis Horizontal Dimensions Vertical Dimensions
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