* Pinout optimizes DDR3 RDIMM PCB layout
* DDR3-800/1066/1333/1600/1866/2133 rate
* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3.

except the open-drain error (ERROUT) output. The clock outputs (Yn and Yn) and control net outputs QnCKEn, QnCSn and Qn.

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation. All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the reset (RESET) and MIRROR inputs which are LVCMOS. A.

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