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IDT74LVC16827A - 3.3V CMOS 20-BIT BUFFER

Description

This 20-bit buffer is built using advanced dual metal CMOS technology.

The LVC16827A provides high-performance bus interface buffering for wide data/address paths or buses carrying parity.

Features

  • Typical tSK(o) (Output Skew) < 250ps.
  • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0).
  • VCC = 3.3V ± 0.3V, Normal Range.
  • VCC = 2.7V to 3.6V, Extended Range.
  • CMOS power levels (0.4μ W typ. static).
  • All inputs, outputs, and I/O are 5V tolerant.
  • Supports hot insertion.
  • Available in TSSOP package DRIVE.

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Datasheet Details

Part number IDT74LVC16827A
Manufacturer IDT
File Size 102.23 KB
Description 3.3V CMOS 20-BIT BUFFER
Datasheet download datasheet IDT74LVC16827A Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O 3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O INDUSTRIALTEMPERATURERANGE IDT74LVC16827A FEATURES: • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in TSSOP package DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM DESCRIPTION: This 20-bit buffer is built using advanced dual metal CMOS technology.
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