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IDT71P74604 - (IDT71P74x04) 18Mb Pipelined QDR II SRAM Burst of 4

Download the IDT71P74604 datasheet PDF. This datasheet also covers the IDT71P74104 variant, as both devices belong to the same (idt71p74x04) 18mb pipelined qdr ii sram burst of 4 family and are provided as variant models within a single manufacturer datasheet.

General Description

Advance Information IDT71P74204 IDT71P74104 IDT71P74804 IDT71P74604 x x x x x x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36) Separate, Independent Read and Write Data Ports Supports concurrent transactions Dual Echo Clock Output 4-Word Burst on all SRAM accesses Multiplexed Address Bus One Read or

Key Features

  • x x x x x x.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT71P74104_IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71P74604
Manufacturer IDT
File Size 323.98 KB
Description (IDT71P74x04) 18Mb Pipelined QDR II SRAM Burst of 4
Datasheet download datasheet IDT71P74604 Datasheet

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Other Datasheets by IDT

Part Number Description
IDT71P74104 (IDT71P74x04) 18Mb Pipelined QDR II SRAM Burst of 4
IDT71P74204 (IDT71P74x04) 18Mb Pipelined QDR II SRAM Burst of 4
IDT71P74804 (IDT71P74x04) 18Mb Pipelined QDR II SRAM Burst of 4
IDT71P71104 (IDT71P71x04) 18Mb Pipelined DDRII SRAM Burst of 2
IDT71P71204 (IDT71P71x04) 18Mb Pipelined DDRII SRAM Burst of 2

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com 18Mb Pipelined QDR™II SRAM Burst of 4 Features x x x x x x Description Advance Information IDT71P74204 IDT71P74104 IDT71P74804 IDT71P74604 x x x x x x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36) Separate, Independent Read and Write Data Ports Supports concurrent transactions Dual Echo Clock Output 4-Word Burst on all SRAM accesses Multiplexed Address Bus One Read or One Write request per clock cycle DDR (Double Data Rate) Data Bus Four word burst data per two clock cycles on each port Four word transfers per clock cycle Depth expansion through Control Logic HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V.