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Integrated Device Technology Electronic Components Datasheet

IDT70V658S Datasheet

HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

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HIGH-SPEED 3.3V
IDT70V659/58/57S
128/64/32K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V659/58/57 easily expands data bus width to 72 bits
or more using the Master/Slave select when cascading
more than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
BE1L
BE0L
BE1R
BE0R
R/WL
CE0L
CE1L
BB BBBBBB
EE EEEEEE
01 233210
L L L L RRRR
R/WR
CE0R
CE1R
OEL
I/O0L- I/O35L
Dout0-8_L
Dout0-8_R
Dout9-17_L Dout9-17_R
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
128/64/32K x 36
MEMORY
ARRAY
Di n_L
Di n_R
OER
I/O0R -I/O35R
A16 L(1)
A0L
Address
Decoder
ADDR_L
ADDR_R
BUSYL(2,3)
SEML
INTL(3)
CE0L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
TDI
TDO
JTAG
NOTES:
1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC's for IDT70V657.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2018 Integrated Device Technology, Inc.
1
Address
Decoder
OER
R/WR
CE0R
CE1R
TMS
TCK
TRST
A16R(1)
A0R
BUSYR(2,3)
SEMR
INTR(3)
4869 drw 01
JUNE 2018
DSC-4869/8


Integrated Device Technology Electronic Components Datasheet

IDT70V658S Datasheet

HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

No Preview Available !

IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V659/58/57 is a high-speed 128/64/32K x 36 Asynchro-
nous Dual-Port Static RAM. The IDT70V659/58/57 is designed to be used
as a stand-alone 4/2/1Mbit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either CE0 or CE1) permit the
on-chip circuitry of each port to enter a very low standby power mode.
The 70V659/58/57 can support an operating voltage of either 3.3V
or 2.5V on one or both ports, controlled by the OPT pins. The power supply
for the core of the device (VDD) remains at 3.3V.
2


Part Number IDT70V658S
Description HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
Maker IDT
Total Page 24 Pages
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